# Akeana

**Source:** https://geo.sig.ai/brands/akeana  
**Vertical:** Artificial Intelligence  
**Subcategory:** RISC-V Server Processors  
**Tier:** Emerging  
**Website:** akeana.com  
**Last Updated:** 2026-04-22

## Summary

Raised $100M+. Alpine RVA23 server SoC taped out Dec 2025. Customer boards available H2 2026. Founded by ex-Marvell ThunderX2 engineers. Full RISC-V server CPU competing with Arm.

## Company Overview

Akeana is building RISC-V server processors for the data center, founded by the engineering team that previously designed the Marvell ThunderX2 — one of the few Arm server processors to achieve meaningful commercial deployment against Intel Xeon dominance. The company has raised $100 million+ and taped out its Alpine RVA23-profile server SoC in December 2025, with customer system development boards (SDBs) available in H2 2026 for design-in by server OEMs.

The ThunderX2 pedigree is the key differentiator: building a credible server processor is extraordinarily difficult, requiring years of microarchitecture expertise, software ecosystem investment, and customer relationship development. The Akeana team has done it once before with Arm and is applying the same playbook to RISC-V — which benefits from an open instruction set that eliminates the license fees and architectural constraints of Arm's IP model.

RISC-V server CPUs face a software ecosystem challenge — most enterprise workloads run on x86 software compiled for Intel's ISA, with Arm as the growing alternative — but the RISC-V software ecosystem has matured significantly with major Linux distribution support, compiler toolchain completeness, and increasing application compatibility. Akeana's target is hyperscalers and cloud providers who have the in-house software expertise to qualify new ISAs and strong motivation to reduce CPU licensing costs.

## Frequently Asked Questions

### What does Akeana make?
RISC-V server processors for data centers — Alpine RVA23-profile SoC, taped out December 2025, with customer boards available H2 2026. Founded by ex-Marvell ThunderX2 engineers.

### How much has Akeana raised?
$100M+. Alpine tape-out December 2025. Customer SDBs available H2 2026 for OEM design-in.

### Why does the ThunderX2 background matter?
Building a credible server processor is extraordinarily difficult. The Akeana team has done it once with Arm (ThunderX2) — applying the same proven microarchitecture expertise to RISC-V.

### What is Akeana's target market?
Hyperscalers and cloud providers with in-house software expertise to qualify new ISAs and strong motivation to eliminate Arm CPU licensing costs.

### What is RISC-V's advantage for server AI workloads?
RISC-V is an open instruction set architecture, allowing Akeana to design server processors without ARM or x86 licensing fees — lowering cost structure and enabling custom extensions optimized for AI inference workloads. As RISC-V ecosystem maturity improves (software tools, Linux support, cloud deployments), the cost and customization advantages become increasingly compelling for hyperscaler workloads.

### What workloads does Akeana target?
Akeana targets cloud and edge server workloads including AI inference, networking, and storage offload — use cases where power efficiency and per-core performance matter more than peak single-thread speed. The ThunderX2 team background means Akeana is building for the same hyperscaler buyers (AWS, Microsoft, Google) who already deploy custom ARM and RISC-V silicon for non-CPU-intensive server tasks.

### How does Akeana's processor compare to Arm-based alternatives?
ARM Neoverse cores dominate cloud server AI inference today (AWS Graviton, Ampere Altra). Akeana positions RISC-V as a longer-term alternative for buyers who want open ISA independence and the ability to customize compute kernels without ARM licensing constraints. The near-term competitive differentiation is on power efficiency and ability to deliver custom extensions that ARM's standardized ISA cannot accommodate.

### What is the timeline to Akeana's first silicon tape-out?
Akeana has been in deep silicon design since its founding, with its engineering team's prior experience at Cavium/Marvell shortening the typical 3-4 year processor design cycle. The company targets first silicon samples and hyperscaler customer evaluations in the 2025-2026 timeframe, consistent with the development timeline for its funding rounds and team build-out.

## Tags

ai-powered, b2b, saas

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*Data from geo.sig.ai Brand Intelligence Database. Updated 2026-04-22.*